1. Field of the Invention
Present invention relates to a semiconductor device, more specifically, to a method of producing a metal-semiconductor field-effect transistor (MESFET).
Preferably, the present invention is applied to a MESFET of a compound semiconductor, e.g., a III-V compound, such as GaAs and InP.
In semiconductor devices such as ICs and LSIs, a miniaturization of the devices is required in order to raise the speed and enhance the performance thereof, as well as to reduce the area of each transistor to thereby increase the integrality thereof. To satisfy these requirements, it is necessary to develop a lithography technique and a self-alignment process by which a pattern having submicron dimensions can be formed.
Furthermore, when a gate length which is directly connected to the characteristics of an FET is shortened, in compliance with the need for miniaturization, the gate resistance (R.sub.G) is usually increased, and therefore, it is necessary to form a gate electrode into a shape such that the resistance is lowered, e.g., by making a sectional area of the gate electrode larger.
2. Description of the Related Art
In a conventional method of producing a MESFET, an active region is defined (element-isolated) by an ion-implantation or a mesa-etching, and thereafter, (1) ohmic electrodes (a source electrode and a drain electrode) are formed to match the active regon, and then a gate electrode is formed to match the ohmic electrodes; or (2) a heat-resistant gate electrode is formed on a portion of the active region, ohmic regions are then self-aligningly formed by an ion-implantation, and thereafter, the ohmic electrodes are formed to match the active region. Nevertheless, since the active region, the ohmic electrodes, and the gate electrode are independently formed in predetermined patterns, a positional deviation of the patterns is liable to occur, and to prevent this defect it is necessary to allow a sufficient clearance for the positioning. Furthermore, the gate length substantially depends upon the lithography technique used, and it is difficult to control the gate length after the lithography step has been carried out. Therefore, to lower the gate resistance, it is necessary to form another larger pattern metal layer on the gate electrode. Further, where the active region is defined (i.e., the isolation region is formed) by the ion-implantation method, the distinction of an implanted region pattern is difficult, and therefore, it is necessary to previously form a suitable matching pattern (alignment pattern) to smooth the process in the subsequent steps.
Heretofore, in the production of a MESFET having a submicron size gate, five or more mask steps are involved in the formation of all of the electrodes of the MESFET and often a positioning (alignment) deviation occurs in the respective steps, and thus it is difficult to control the device characteristics of the MESFET. further, since the gate length of the MESFET substantially depends upon the lithography technique used, a gate length having a size smaller than the gate pattern size of the mask cannot be obtained.